I. Field of the Disclosure
The technology of the disclosure relates generally to phase locked loops (PLLs) shared by multiple devices.
II. Background
Circuits within computing devices generally communicate through a bus according to a particular bus standard (e.g., Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB) version 3 (USB3), etc.). The interface between the circuits and the bus is generally known as a physical layer (PHY) of a communication protocol stack used by the circuits to communicate. The PHY is the first layer of the Open System Interconnection Model (OSI Model). The PHY deals with bit-level transmission between different devices and supports electrical or mechanical interfaces connecting to the physical medium for synchronized communication.
A bus operating according to a particular bus standard may have multiple links for connecting integrated circuits (ICs) of a system (for example, a central processing unit (CPU), memory, communication modules, etc.). A PHY port on a first IC transmits and/or receives, for example, data packets to and/or from a PHY port on a second IC through a corresponding link. The two ports that comprise a communication link may have one or more lanes; each lane is used as a full-duplex communication channel between the first and second ICs. The throughput between the first and second ICs may be increased by increasing the number of lanes of the corresponding link. When using multiple lanes, the data packets transmitted through the multi-lane link may be interleaved across the multiple lanes by a transmitting element and reassembled at a receiving element.
In some instances, the PHY of an IC using the bus may be a multi-port PHY. Each port of the multi-port PHY is configured to operate independently from other ports of the multi-port PHY. Each port is connected to a distinct link of the bus, such that each port may work concurrently with, but independently from, the other ports of the multi-port PHY. In many instances, the multiple ports of the multi-port PHY will need a clock signal for communicating through their corresponding links. Accordingly, each port will include a phase locked loop (PLL) and other clock logic to generate a corresponding clock signal. However, having a PLL and other clock logic for each port increases the area and power consumption in the IC. Therefore, in applications where area and power consumption are limited, some or all ports of an IC's multi-port PHY may be configured to share a single PLL, thus providing for reduced semiconductor area and power consumption.
Sharing the PLL, however, may lead to problems, as an unexpected variation in the shared PLL may affect one or more of the ports sharing the PLL. For example, if a port of the multi-port PHY causes a reset or re-initialization of the shared PLL, some or all of the other ports sharing the PLL may experience communication errors and/or loss of data.